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rt8024 1 ds8024-02 march 2011 www.richtek.com features z z z z z 2.5v to 5.5v input range z z z z z adjustable output from 0.6v to v in z z z z z 1.0v, 1.2v, 1.5v, 1.8v, 2.5v and 3.3v fixed/ adjustable output voltage z z z z z 400ma output current, 1a peak current z z z z z 95% efficiency z z z z z no schottky diode required z z z z z 1.5mhz fixed frequency pwm operation z z z z z small sot-23-5 and tsot-23-5 package z z z z z rohs compliant and halogen free applications z cellular telephones z personal information appliances z wireless and dsl modems z mp3 players z portable instruments 1.5mhz, 400ma, high efficiency pwm step-down dc/dc converter general description the rt8024 is a high-efficiency pulse-width-modulated (pwm) step-down dc/dc converter. capable of delivering 400ma output current over a wide input voltage range from 2.5v to 5.5v, the rt8024 is ideally suited for portable electronic devices that are powered from 1-cell li-ion battery or from other power sources within the range such as cellular phones, pdas and handy-terminals. internal synchronous rectifier with low r ds(on) dramatically reduces conduction loss at pwm mode. no external schottky diode is required in practical application. the rt8024 automatically turns off the synchronous rectifier while the inductor current is low and enters discontinuous pwm mode. this can increase efficiency at light load condition. the rt8024 enters low-dropout mode when normal pwm cannot provide regulated output voltage by continuously turning on the upper p-mosfet. rt8024 enter shutdown mode and consumes less than 0.1 a when en pin is pulled low. the switching ripple is easily smoothed-out by small package filtering elements due to a fixed operation frequency of 1.5mhz. this along with small sot-23-5 and tsot-23-5 package provides small pcb area application. other features include soft start, lower internal reference voltage with 2% accuracy, over temperature protection, and over current protection. note : richtek products are : ` rohs compliant and compatible with the current require- ments of ipc/jedec j-std-020. ` suitable for use in snpb or pb-free soldering processes. ordering information pin configurations (top view) sot-23-5/tsot-23-5 en gnd lx fb/vout vin 4 23 5 rt8024(- ) package type b : sot-23-5 j5 : tsot-23-5 output voltage default : adjustable 10 : 1.0v 12 : 1.2v 15 : 1.5v 18 : 1.8v 25 : 2.5v 33 : 3.3v lead plating system g : green (halogen free and pb free) marking information for marking information, contact our sales representative directly or through a richtek distributor located in your area.
rt8024 2 ds8024-02 march 2011 www.richtek.com layout note: 1. the distance that c in connects to v in is as close as possible (under 2mm). 2. c out should be placed near rt8024. typical application circuit figure 1. fixed voltage regulator figure 2. adjustable voltage regulator ? ? ? ? ? ? + = r2 r1 1 x v v ref out with r2 = 300k to 60k so the i r2 = 2 a to 10 a, and (r1 x c1) should be in the range between 3x10 -6 and 6x10 -6 for component selection. layout guide figure 3 en gnd lx vout 2 3 5 4 1 vin gnd v in v out c out c in gnd l en gnd lx fb 2 3 5 4 1 vin gnd v in v out c out c in gnd c1 r1 r2 l v out 4.7f 10f vin lx gnd rt8024 en vout 2.2h 2.2v to 5.5v v in v out c in l 5 3 4 1 2 c out 4.7f 10f vin lx gnd rt8024 en fb 2.2h 2.2v to 5.5v v in v out c in l 5 3 4 1 2 c out r1 r2 c1 i r2
rt8024 3 ds8024-02 march 2011 www.richtek.com functional pin description pin no. pin name pin function 1 en chip enable (active high, do not leave en pin floating, and v en < v in + 0.6v). 2 gnd ground. 3 lx pin for switching. 4 vin power input. 5 fb/vout feedback input pin. function block diagram comp rc rs1 rs2 en vin lx fb/vout uvlo & power good detector v ref slope compensation current sense osc & shutdown control zero detector current limit detector driver control logic pwm comparator error amplifier gnd
rt8024 4 ds8024-02 march 2011 www.richtek.com absolute maximum ratings (note 1) supply input v oltage ------------------------------------------------------------------------------------------------------ 6.5v enable, fb voltage ------------------------------------------------------------------------------------------------------- v in + 0.6v power dissipation, p d @ t a = 25 c sot-23-5, tsot-23-5 ----------------------------------------------------------------------------------------------------- 0.4w package thermal resistance (note 2) sot-23-5, tsot-23-5, ja ----------------------------------------------------------------------------------------------- 250 c/w sot-23-5, tsot-23-5, jc ----------------------------------------------------------------------------------------------- 130 c/w junction temperature range -------------------------------------------------------------------------------------------- 150 c lead temperature (soldering, 10 se c.) ------------------------------------------------------------------------------- 260 c storage temperature range -------------------------------------------------------------------------------------------- ? 65 c to 150 c esd susceptibility (note 3) hbm (human body mode) ---------------------------------------------------------------------------------------------- 2kv mm (ma chine mode) ------------------------------------------------------------------------------------------------------ 200v electrical characteristics (v in = 3.6v, v out = 2.5v, v ref = 0.6v, l = 2.2 h, c in = 4.7 f, c out = 10 f, t a = 25 c, i max = 400ma unless otherwise specified) parameter symbol test conditions min typ max unit input voltage range v in 2.5 -- 5.5 v quiescent current i q i out = 0ma, v fb = v ref + 5% -- 50 100 a shutdown current i shdn en = gnd -- 0.1 1 a reference voltage v ref for adjustable output voltage 0.588 0.6 0.612 v adjustable output range v out v ref -- v in ? 0.2 v v ou t v in = 2.2 to 5.5v, v ou t = 1.0v 0a < i out < 400ma ? 3 -- 3 % v ou t v in = 2.2 to 5.5v, v ou t = 1.2v 0a < i out < 400ma ? 3 -- 3 % v ou t v in = 2.2 to 5.5v, v ou t = 1.5v 0a < i out < 400ma ? 3 -- 3 % v ou t v in = 2.2 to 5.5v, v ou t = 1.8v 0a < i out < 400ma ? 3 -- 3 % v ou t v in = 2.8 to 5.5v, v ou t = 2.5v 0a < i out < 400ma ? 3 -- 3 % fix v ou t v in = 3.5 to 5.5v, v ou t = 3.3v 0a < i out < 400ma ? 3 -- 3 % v in = v out + 0.2v to 5.5v, v in R 3.5v 0a < i out < 400ma ? 3 -- 3 % output voltage accuracy adjustable v ou t v in = v out + 0.4v to 5.5v, v in R 2.2v 0a < i out < 400ma ? 3 -- 3 % to be continued recommended operating conditions (note 4) supply input v oltage ------------------------------------------------------------------------------------------------------ 2.5v to 5.5v junction temperature range -------------------------------------------------------------------------------------------- ? 40 c to 125 c ambient temperature range -------------------------------------------------------------------------------------------- ? 40 c to 85 c
rt8024 5 ds8024-02 march 2011 www.richtek.com parameter symbol test conditions min typ max unit fb input current i fb v fb = v in ? 50 -- 50 na v in = 3.6v -- 0.3 -- pmosfet r on p rds(on) i out = 200ma v in = 2.5v -- 0.4 -- v in = 3.6v -- 0.25 -- nmosfet r on n rds(on) i out = 200ma v in = 2.5v -- 0.35 -- p-channel current limit i p( lm) v in = 2.5v to 5.5 v 1 -- 1.8 a en high-level input voltage v enh v in = 2.5v to 5.5v 1.5 -- -- v en low-level input voltage v enl v in = 2.5v to 5.5v -- -- 0.4 v undervoltage lock out threshold -- 1.8 -- v hysteresis -- 0.1 -- v oscillator frequency f osc v in = 3.6v, i out = 100ma 1.2 1.5 1.8 mhz thermal shutdown temperature t sd -- 160 -- c min. on time -- 50 -- ns max. duty cycle 100 -- -- % lx leakage current v in = 3.6v, v lx = 0v or v lx = 3.6v ? 1 -- 1 a note 1. stresses listed as the above ? absolute maximum ratings ? may cause permanent damage to the device. these are for stress ratings. functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. note 2. ja is measured in the natural convection at t a = 25 c on a low effective single layer thermal conductivity test board of jedec 51-3 thermal measurement standard. pin 2 of sot-23-5/tsot-23-5 packages is the case position for jc measurement. note 3. devices are esd sensitive. handling precaution is recommended. note 4. the device is not guaranteed to function outside its operating conditions.
rt8024 6 ds8024-02 march 2011 www.richtek.com reference voltage vs. input voltage 0.5990 0.5995 0.6000 0.6005 0.6010 2.5 3 3.5 4 4.5 5 5.5 input voltage (v) reference voltage (v) v out = 1.2v typical operating characteristics efficiency vs. load current 40 50 60 70 80 90 100 0.01 0.11 0.21 0.31 0.41 0.51 0.61 load current (a) efficiency (%) v in = 5v v in = 3.3v v out = 1.2v current limit vs. input voltage 0.0 0.5 1.0 1.5 2.0 2.5 2.533.544.555.5 input voltage (v) current limit (a) v out = 1.2v frequency vs. input voltage 1.35 1.38 1.40 1.43 1.45 1.48 1.50 2.5 3 3.5 4 4.5 5 5.5 input voltage (v) frequency (mhz) v out = 1.2v, i out = 300ma frequency vs. temperature 1.30 1.33 1.35 1.38 1.40 1.43 1.45 1.48 1.50 -50 -25 0 25 50 75 100 125 temperature frequency (mhz ) ( c) v out = 1.2v, i out = 300ma output voltage vs. load current 1.180 1.185 1.190 1.195 1.200 1.205 1.210 1.215 1.220 0.01 0.11 0.21 0.31 0.41 0.51 0.61 load current (a) output voltage (v) v in = 5v v in = 3.3v v out = 1.2v v in = 2.5v
rt8024 7 ds8024-02 march 2011 www.richtek.com output voltage vs. temperature 1.15 1.17 1.19 1.21 1.23 1.25 -50 -25 0 25 50 75 100 125 temperature output voltage (v) ( c) v in = 3.3v, i out = 0a output ripple time (500ns/div) i lx (500ma/div) v lx (5v/div) v in = 3.3v, v out = 1.2v, i out = 400ma v out (5mv/div) power off time (100 s/div) i in (200ma/div) v out (1v/div) v in = 3.3v, v out = 1.2v, i out = 400ma v en (5v/div) load transient response time (50 s/div) i out (200ma/div) v out (20mv/div) v in = 3.3v, v out = 1.2v, i out = 200ma to 400ma load transient response time (50 s/div) i out (200ma/div) v out (20mv/div) v in = 3.3v, v out = 1.2v, i out = 100ma to 400ma power on time (100 s/div) i in (200ma/div) v out (1v/div) v in = 3.3v, v out = 1.2v, i out = 400ma v en (5v/div)
rt8024 8 ds8024-02 march 2011 www.richtek.com applications information the basic rt8024 application circuit is shown in typical application circuit. external component selection is determined by the maximum load current and begins with the selection of the inductor value and operating frequency followed by c in and c out . inductor selection for a given input and output voltage, the inductor value and operating frequency determine the ripple current. the ripple current i l increases with higher v in and decreases with higher inductance. having a lower ripple current reduces the esr losses in the output capacitors and the output voltage ripple. highest efficiency operation is achieved at low frequency with small ripple current. this, however, requires a large inductor. a reasonable starting point for selecting the ripple current is i l = 0.4(i max ). the largest ripple current occurs at the highest v in . to guarantee that the ripple current stays below a specified maximum, the inductor value should be chosen according to the following equation : inductor core selection once the value for l is known, the type of inductor must be selected. high efficiency converters generally cannot afford the core loss found in low cost powdered iron cores, forcing the use of more expensive ferrite or mollypermalloy cores. actual core loss is independent of core size for a fixed inductor value but it is very dependent on the inductance selected. as the inductance increases, core losses decrease. unfortunately, increased inductance requires more turns of wire and therefore copper losses will increase. ferrite designs have very low core losses and are preferred at high switching frequencies, so design goals can concentrate on copper loss and preventing saturation. ferrite core material saturates ? hard ? , which means that inductance collapses abruptly when the peak design ? ? ? ? ? ? ? ? ? ? ? ? ? = in out out l v v 1 l f v i ? ? ? ? ? ? ? ? ? ? ? ? ? = in(max) out l(max) out v v 1 i f v l current is exceeded. this results in an abrupt increase in inductor ripple current and consequent output voltage ripple. do not allow the core to saturate! different core materials and shapes will change the size/ current and price/current relationship of an inductor. toroid or shielded pot cores in ferrite or permalloy materials are small and don ? t radiate energy but generally cost more than powdered iron core inductors with similar characteristics. the choice of which style inductor to use mainly depends on the price vs size requirements and any radiated field/emi requirements. c in and c out selection the input capacitance, c in , is needed to filter the trapezoidal current at the source of the top mosfet. to prevent large ripple voltage, a low esr input capacitor sized for the maximum rms current should be used. rms current is given by : 1 v v v v i i out in in out out(max) rms ? = this formula has a maximum at v in = 2v out , where i rms = i out /2. this simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. note that ripple current ratings from capacitor manufacturers are often based on only 2000 hours of life which makes it advisable to further derate the capacitor, or choose a capacitor rated at a higher temperature than required. several capacitors may also be paralleled to meet size or height requirements in the design. the selection of c out is determined by the effective series resistance (esr) that is required to minimize voltage ripple and load step transients, as well as the amount of bulk capacitance that is necessary to ensure that the control loop is stable. loop stability can be checked by viewing the load transient response as described in a later section. the output ripple, v out , is determined by : ? ? ? ? ? ? + out l out 8fc 1 esr i v the output ripple is highest at maximum input voltage since i l increases with input voltage. multiple capacitors placed in parallel may be needed to meet the esr and rms current handling requirements. dry tantalum, special
rt8024 9 ds8024-02 march 2011 www.richtek.com output voltage programming the resistive divider allows the v fb pin to sense a fraction of the output voltage as shown in figure 4. ) r2 r1 (1 v v ref out + = figure 4. setting the output voltage where v ref is the internal reference voltage (0.6v typ.) efficiency considerations the efficiency of a switching regulator is equal to the output power divided by the input power times 100%. it is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. efficiency can be expressed as : efficiency = 100% ? (l1+ l2+ l3+ ...) where l1, l2, etc. are the individual losses as a percentage of input power. although all dissipative elements in the circuit produce losses, two main sources usually account for most of the losses : vin quiescent current and i 2 r losses. the vin quiescent current loss dominates the efficiency loss at very low load currents whereas the i 2 r loss dominates the efficiency loss at medium to high load currents. in a typical efficiency plot, the efficiency curve at very low load currents can be misleading since the actual power lost is of no consequence. 1. the vin quiescent current is due to two components : the dc bias current as given in the electrical characteristics and the internal main switch and synchronous switch gate charge currents. the gate charge current results from switching the gate capacitance of the internal power mosfet switches. each time the gate is switched from high to low to high again, a packet of charge q moves from v in to ground. the resulting q/ t is the current out of v in that is typically larger than the dc bias current. in continuous mode, i gatechg = f(q t +q b ) where q t and q b are the gate charges of the internal top and bottom switches. both the dc bias and gate charge losses are proportional to v in and thus their effects will be more pronounced at higher supply voltages. 2. i 2 r losses are calculated from the resistances of the internal switches, r sw and external inductor r l . in continuous mode the average output current flowing through inductor l is ? chopped ? between the main switch and the synchronous switch. thus, the series resistance looking into the lx pin is a function of both top and bottom mosfet r ds(on) and the duty cycle (dc) as follows : r sw = r ds(on)top x dc + r ds(on)bot x (1 ? dc) the r ds(on) for both the top and bottom mosfets can be obtained from the typical performance characteristics for adjustable about voltage mode, the output voltage is set by an external resistive divider according to the following equation : rt8024 gnd fb r1 r2 v out polymer, aluminum electrolytic and ceramic capacitors are all available in surface mount packages. special polymer capacitors offer very low esr but have lower capacitance density than other types. tantalum capacitors have the highest capacitance density but it is important to only use types that have been surge tested for use in switching power supplies. aluminum electrolytic capacitors have significantly higher esr but can be used in cost-sensitive applications provided that consideration is given to ripple current ratings and long term reliability. ceramic capacitors have excellent low esr characteristics but can have a high voltage coefficient and audible piezoelectric effects. the high q of ceramic capacitors with trace inductance can also lead to significant ringing. using ceramic input and output capacitors higher values, lower cost ceramic capacitors are now becoming available in smaller case sizes. their high ripple current, high voltage rating and low esr make them ideal for switching regulator applications. however, care must be taken when these capacitors are used at the input and output. when a ceramic capacitor is used at the input and the power is supplied by a wall adapter through long wires, a load step at the output can induce ringing at the input, v in . at best, this ringing can couple to the output and be mistaken as loop instability. at worst, a sudden inrush of current through the long wires can potentially cause a voltage spike at v in large enough to damage the part.
rt8024 10 ds8024-02 march 2011 www.richtek.com curves. thus, to obtain i 2 r losses, simply add r sw to r l and multiply the result by the square of the average output current. other losses including c in and c out esr dissipative losses and inductor core losses generally account for less than 2% of the total loss. thermal considerations the maximum power dissipation depends on the thermal resistance of ic package, pcb layout, the rate of surroundings airflow and temperature difference between junction to ambient. the maximum power dissipation can be calculated by following formula : p d(max) = ( t j(max) - t a ) / ja where t j(max) is the maximum operation junction temperature 125 c, t a is the ambient temperature and the ja is the junction to ambient thermal resistance. for recommended operating conditions specification of rt8024 dc/dc converter, where t j (max) is the maximum junction temperature of the die (125 c) and t a is the maximum ambient temperature. the junction to ambient thermal resistance ja is layout dependent. for sot-23-5/tsot-23-5 packages, the thermal resistance ja is 250 c/w on the standard jedec 51-3 single-layer thermal test board. the maximum power dissipation at t a = 25 c can be calculated by following formula : p d(max) = ( 125 c - 25 c ) / 250 = 0.4 w for sot-23-5/ tsot-23-5 packages the maximum power dissipation depends on operating ambient temperature for fixed t j(max) and thermal resistance ja . for rt8024 packages, the figure 5 of derating curves allows the designer to see the effect of rising ambient temperature on the maximum power allowed. the value of junction to case thermal resistance jc is popular for users. this thermal parameter is convenient for users to estimate the internal junction operated temperature of packages while ic operating. it's independent of pcb layout, the surroundings airflow effects and temperature difference between junction to ambient. the operated junction temperature can be calculated by following formula : t j = t c + p d x jc where t c is the package case (pin 2 of package leads) temperature measured by thermal sensor, p d is the power dissipation defined by user's function and the jc is the junction to case thermal resistance provided by ic manufacturer. therefore it's easy to estimate the junction temperature by any condition. checking transient response the regulator loop response can be checked by looking at the load transient response. switching regulators take several cycles to respond to a step in load current. when a load step occurs, v out immediately shifts by an amount equal to i load (esr), where esr is the effective series resistance of c out . i load also begins to charge or discharge c out generating a feedback error signal used by the regulator to return v out to its steady-state value. during this recovery time, v out can be monitored for overshoot or ringing that would indicate a stability problem. layout considerations follow the pcb layout guidelines for optimal performance of rt8024. ` for the main current paths as indicated in bold lines in figure 6, keep their traces short and wide. ` put the input capacitor as close as possible to the device pins (vin and gnd). ` lx node is with high frequency voltage swing and should be kept small area. keep analog components away from lx node to prevent stray capacitive noise pick-up. figure 5. derating curves for rt8024 package 0 50 100 150 200 250 300 350 400 450 0 20 40 60 80 100 120 140 ambient temperature (c) maximum power dissipation (mw) single layer pcb sot-23-5, tsot-23-5 packages
rt8024 11 ds8024-02 march 2011 www.richtek.com } connect feedback network behind the output capacitors. keep the loop area small. place the feedback components near the rt8024. } connect all analog grounds to a command node and then connect the command node to the power ground behind the output capacitors. figure 6. evb schematic lx gnd rt8024 en fb l1 c4 v in v out c3 r1 r2 vin v in 4 1 2 3 5 10uf c1 c2 j1 suggested inductors suggested capacitors for c in and c out component supplier series inductance ( m h) dcr (m w ) current rating (ma) dimensions (mm) taiyo yuden nr 3015 2.2 60 1480 3 x 3 x 1.5 taiyo yuden nr 3015 4.7 120 1020 3 x 3 x 1.5 sumida cdrh2d14 2.2 75 1500 4.5 x 3.2 x 1.55 sumida cdrh2d14 4.7 135 1000 4.5 x 3.2 x 1.55 gotrend gtsd32 2.2 58 1500 3.85 x 3.85 x 1.8 gotrend gtsd32 4.7 146 1100 3.85 x 3.85 x 1.8 component supplier part no. capacitance ( m f) case size tdk c1608jb0j475m 4.7 0603 tdk c2012jb0j106m 10 0805 murata grm188r60j475ke19 4.7 0603 murata grm219r60j106me19 10 0805 murata grm219r60j106ke19 10 0805 taiyo yuden JMK107BJ475RA 4.7 0603 taiyo yuden jmk107bj106ma 10 0603 taiyo yuden jmk212bj106rd 10 0805
rt8024 12 ds8024-02 march 2011 www.richtek.com outline dimension a a1 e b b d c h l sot-23-5 surface mount package dimensions in millimeters dimensions in inches symbol min max min max a 0.889 1.295 0.035 0.051 a1 0.000 0.152 0.000 0.006 b 1.397 1.803 0.055 0.071 b 0.356 0.559 0.014 0.022 c 2.591 2.997 0.102 0.118 d 2.692 3.099 0.106 0.122 e 0.838 1.041 0.033 0.041 h 0.080 0.254 0.003 0.010 l 0.300 0.610 0.012 0.024
rt8024 13 ds8024-02 march 2011 www.richtek.com richtek technology corporation headquarter 5f, no. 20, taiyuen street, chupei city hsinchu, taiwan, r.o.c. tel: (8863)5526789 fax: (8863)5526611 information that is provided by richtek technology corporation is believed to be accurate and reliable. richtek reserves the ri ght to make any change in circuit design, specification or other related things if necessary without notice at any time. no third party intellectual property inf ringement of the applications should be guaranteed by users when integrating richtek products into any application. no legal responsibility for any said applications i s assumed by richtek. richtek technology corporation taipei office (marketing) 5f, no. 95, minchiuan road, hsintien city taipei county, taiwan, r.o.c. tel: (8862)86672399 fax: (8862)86672377 email: marketing@richtek.com tsot-23-5 surface mount package dimensions in millimeters dimensions in inches symbol min max min max a 0.700 1.000 0.028 0.039 a1 0.000 0.100 0.000 0.004 b 1.397 1.803 0.055 0.071 b 0.300 0.559 0.012 0.022 c 2.591 3.000 0.102 0.118 d 2.692 3.099 0.106 0.122 e 0.838 1.041 0.033 0.041 h 0.080 0.254 0.003 0.010 l 0.300 0.610 0.012 0.024 a a1 e b b d c h l

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